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PIC18F6585/8585/6680/8680
DS30491C-page 298
2004 Microchip Technology Inc.
REGISTER 23-23: BnCON: TX/RX BUFFER n CONTROL REGISTERS IN TRANSMIT MODE
[0
≤ n ≤ 5, TXnEN (BSEL0<n>) = 1](1)
R/W-0
R-0
R/W-0
TXBIF
TXABT
TXLARB
TXERR
TXREQ
RTREN
TXPRI1
TXPRI0
bit 7
bit 0
bit 7
TXBIF: Transmit Buffer Interrupt Flag bit(1)
1
= A message is successfully transmitted
0
= No message was transmitted
bit 6
TXABT: Transmission Aborted Status bit(1)
1
= Message was aborted
0
= Message was not aborted
bit 5
TXLARB: Transmission Lost Arbitration Status bit(2)
1
= Message lost arbitration while being sent
0
= Message did not lose arbitration while being sent
bit 4
TXERR: Transmission Error Detected Status bit(2)
1
= A bus error occurred while the message was being sent
0
= A bus error did not occur while the message was being sent
bit 3
TXREQ: Transmit Request Status bit(3)
1
= Requests sending a message; clears the TXABT, TXLARB, and TXERR bits
0
= Automatically cleared when the message is successfully sent
Note:
Clearing this bit in software while the bit is set will request a message abort.
bit 2
RTREN: Automatic Remote Transmission Request Enable bit
1
= When a remote transmission request is received, TXREQ will be automatically set
0
= When a remote transmission request is received, TXREQ will be unaffected
bit 1-0
TXPRI1:TXPRI0: Transmit Priority bits(4)
11
= Priority Level 3 (highest priority)
10
= Priority Level 2
01
= Priority Level 1
00
= Priority Level 0 (lowest priority)
Note 1: These registers are available in Mode 1 and 2 only.
2: This bit is automatically cleared when TXREQ is set.
3: While TXREQ is set or transmission is in progress, transmit buffer registers remain
read-only.
4: These bits set the order in which the transmit buffer will be transferred. They do not
alter the CAN message identifier.
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
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